Computer · Computer Basics · Topic 1 of 16
Computer Organization and the CPU
Think of it like…
A kirana shopkeeper billing a grocery chit
Ramesh runs a kirana shop in a Kolhapur galli. A customer hands him a chit: "1 kg sugar, 2 packets Parle-G, 500 g toor dal". Ramesh keeps his finger on the line he must do next. He reads that line (fetch), understands what it means — which shelf, how much (decode) — then weighs the item and adds its price to the running total on his small slate (execute). His finger moves to the next line and the cycle repeats until the chit ends. The chit is the program sitting in memory; his finger is the Program Counter; his brain, which understands each line and tells his hands what to do, is the Control Unit; the calculator is the ALU; and the slate holding the running total is a register (the accumulator). Notice that his brain never weighs or adds anything itself — it only directs. That is exactly the Control Unit.
| In everyday life | In the exam topic |
|---|---|
| The customer’s chit (items in order) | Program stored in main memory |
| Finger on the line to be done next | Program Counter (PC) |
| The line he is reading right now | Instruction Register (IR) |
| His brain: understands the line, directs his hands | Control Unit — decodes and sends control signals |
| Calculator + slate with the running total | ALU + accumulator register |
The concept
Almost every computer follows the von Neumann (stored-program) model: the program and its data sit together in main memory, and the CPU fetches instructions one at a time. The machine has five functional units — input, memory, ALU, control unit, output. The CPU is the ALU + control unit + registers, on one chip.
The ALU (Arithmetic Logic Unit) does arithmetic (+, −) and logic (AND, OR, NOT, compare). The Control Unit processes no data at all: it decodes each instruction and sends control signals (memory read, memory write, which ALU operation) to every other unit, in step with the clock. Registers are tiny, fastest storage inside the CPU: PC, IR, MAR, MDR (also called MBR), the accumulator and the flag (status) register.
The CPU repeats the instruction cycle forever: fetch (MAR ← PC; MDR ← M[MAR]; IR ← MDR; PC ← PC + 1), decode (the CU reads the opcode), execute (ALU, memory or I/O action; flags updated). Then it checks for interrupts and starts again. Speed is set by the clock: a 2 GHz clock gives 2 × 10⁹ cycles per second, so one cycle lasts 0.5 ns.
Key points & formulas
- CPU = ALU + Control Unit + registers; the CU directs, the ALU computes
- PC: address of the next instruction; IR: the instruction being executed now
- MAR: address sent to memory; MDR/MBR: data coming from or going to memory
- Accumulator holds ALU results; flag register holds Zero, Sign, Carry, Overflow bits
- Fetch: MAR ← PC → MDR ← M[MAR] → IR ← MDR, PC ← PC + 1
- Clock period = 1 ÷ frequency; instruction time = cycles × period
- Von Neumann: one memory for program and data (the “von Neumann bottleneck”); Harvard: separate instruction and data memories
- Control unit design: hardwired (fast, fixed logic) or microprogrammed (control memory, easy to change)
Worked example
Memory holds a program at addresses 100–102: LOAD 500, ADD 501, STORE 502. M[500] = 7 and M[501] = 5. The PC starts at 100. Trace the registers. What are M[502] and the PC at the end?
Show solution
- Fetch 1: MAR ← 100, IR ←
LOAD 500, PC ← 101. Execute: AC ← M[500] = 7. - Fetch 2: MAR ← 101, IR ←
ADD 501, PC ← 102. Execute: the ALU adds, AC ← 7 + M[501] = 12. - Fetch 3: MAR ← 102, IR ←
STORE 502, PC ← 103. Execute: M[502] ← AC = 12. - The PC is incremented during every fetch, so after three instructions it points to 103.
Answer: M[502] = 12, PC = 103
Exam shortcut
For “which register” questions ask: is it an address or a content? Addresses live in the PC and MAR; contents live in the IR, MDR and accumulator. For clock questions, period in ns = 1 ÷ (GHz value): 2.5 GHz → 0.4 ns.
Common traps
- The PC holds the address of the next instruction, not the current one (it is incremented during fetch).
- The Control Unit does no calculation; even a comparison such as a < b is done by the ALU.
Practice · tap an option to check
Q1. Which register holds the address of the next instruction to be fetched?
Answer: B. The PC always points to the next instruction; the IR holds the one being executed.
Q2. Which sequence correctly describes the fetch phase of the instruction cycle?
Answer: D. The address goes PC → MAR, memory returns the word into MDR, it is copied into IR, and the PC is incremented.
Q3. Which unit of the CPU interprets instructions and generates timing and control signals, but does not itself process data?
Answer: A. The CU decodes and directs; all data processing is done by the ALU.
Q4. A processor runs at 2.5 GHz. An instruction needs 5 clock cycles. How long does the instruction take?
Answer: C. Clock period = 1 ÷ 2.5 GHz = 0.4 ns. Time = 5 × 0.4 ns = 2 ns.